Catena: A Near-Threshold, Sub-0.4-mW, 16-Core Programmable Spatial Array Accelerator for the Ultralow-Power Mobile and Embedded Internet of Things
Joao Pedro Cerqueira, Thomas J. Repetti, Yu Pu, Shivam Priyadarshi, Martha A. Kim, Mingoo Seok · IEEE Journal of Solid-State Circuits · 2020
In this article, we present Catena, a near-threshold voltage 16-core programmable spatial array accelerator supporting workloads for ultralow-power (ULP) mobile and embedded Internet of Things applications. We observe that employing supply voltage scaling alone in a large-scale, massively parallel spatial architecture, such as Catena, results in marginal runtime energy efficiency. The reason is that ultralow-voltage operation magnifies the energy waste of underutilized and always-on hardware in portion to the system's total energy consumption. Hence, we propose circuit and architecture techniques to minimize such energy waste and extend the energy efficiency of our spatial array accelerator architecture. To demonstrate the effectiveness of the proposed techniques, we design and prototype Catena in a 65-nm low-power CMOS. Our prototype achieves 228 pJ/cycle. As compared to a spatial-like architecture running the same workload, Catena achieves 2.7× higher energy efficiency.