Multiplexer based Voltage Controlled Delay Buffer Element
Pooja Saxena, Mohammad Amir Khan · 2019
This paper presents a voltage controlled delay buffer using a 2:1 multiplexer, designed in 0.35 μm CMOS process. The multiplexer is realized with transmission gate, which results in achievement of high speed, low power and full swing output characteristics of delay buffer. The least attained post layout rising edge delay is 120 ps that is comparable with standard cell inverter. The delay regulation range achieved over control voltage of 0 V to 3.3 V is from 120ps to 560ps. The performance of delay buffer for single edge delay control across PVT variations is successfully verified by design of modified delay lock loop.