Self-Timed Multiply-add-subtract Unit Alternates
Yu. A. Stepchenkov, Yuri Diachenko, Yury V. Rogdestvenski, Denis Y. Diachenko, Yury I. Shikunov · 2020
Paper presents the results of a study of the self-timed fused multiply-add-subtract unit (FMAS) alternates. All FMAS alternates comply with the IEEE 754 standard and use the modified Booth algorithm to multiply two input 64-bit operands, followed by the addition and subtraction of the third operand. They differ from each other by internal signals self-timed coding: dual-rail, redundant ternary, or redundant quaternary code. The paper analyzes and compares their features, offers their optimized pipeline implementations and recommendations for their use. FMAS alternates have approximately the same performance but different hardware costs and layout sizes.