FPGA Implementation of Digital Processing Blocks Using Optimal Resolution Multipliers
Alexey A. Biryuk, Marat S. Khasanov, Ilya A. Kuzmin, Yury M. Meleshin · 2020
The paper proposes an architecture of lossy multiplier for FPGA implementation. The proposed multiplier requires less logic resources but produces some error. This multiplier is being studied as a part of digital processing blocks: FIR-filters and FFT-processor. The results are verified using mathematical modeling tools and FPGA synthesis tools.