SERDES Transceiver for Supply-Induced Jitter Sensitivity Methodology Based on PDN analysis
Michael Chang · 2019
Chip-package-printed circuit board co-design has been attracting attention recently as a design methodology in development. One of the most important elements is to present detailed analysis of supply induced jitter sensitivity of Serdes transceiver. General SERDES transmitter architecture is serial-to-parallel converter and is sensitive to supply noise. The SERDES transmitter has power domains that have different influences in the jitter-sensitivity contribution of analog circuits. The jitter sensitivity is dependent of each circuit block silicon characterization and combined with Data/CLK path. It explains the jitter sensitivity contribution of each analog block circuit and provides a solution to its individual challenge. With jitter sensitivity extraction of analog block circuit (PLL/Duty cycle corrector/clock tree/parallel to serial/2to1/pre-driver/current mode IO), it is possible to enable accurate jitter-aware target impedance calculation. It gives the in-depth SI/PI insight into analog design field and optimization/achieving on silicon success.