Throughput Logic Simulation by Quartus Prime State Machine
Artem Vladimirovich Grekov, Sergey Feofentovich Tyurin · 2020
The paper proposes and investigates the automatic synthesis of a throughput logic simulation by Quartus Prime state machine option and VHDL. For the combinational finite state machine, we have only one state and many arcs. Product terms prepared from the corresponding truth table, which must be obtained before using the State Machine Editor Quartus Prime. Are presented the results of a study the LUT FPGA truth tables too.