Optimized Microcode BIST Architecture for Multiple Memory Cores in SoCs
Anitta Paul, P Rony Antony · 2018
The ongoing advancements in IC technology results in increasing the capacity and density of memories in SoC's. The testing time, area overhead and cost of the test plays an important role during testing of memories. Built-in self-test (BIST) is a self testing mechanism that allows testing of multiple memory cores of different sizes. The parallel testing approach reduce the test time of memories. The area overhead reduces at a reasonable limit by using a single response analyzer instead of using individual modules for each memories. By changing the instructions in the Microcode controller storage unit, new march algorithms can be implemented without redesign the circuitry. This paper proposes an efficient method for testing multiple Memory cores of different sizes in parallel form without much increase in area of SoCs. The proposed Microcode BIST utilizes less area overhead and the time utilization compared with existing parallel architecture. Xilinx ISE 14.2 is used to implement the architecture.