Implementation of Recursive Formulation for Parallel Self-Timed Adder using Verlog Logic
Siva Kumar M · International Journal of Emerging Trends in Engineering Research · 2020
In the brief implementation presents a parallel self-time adder in recursive approach of multi bit binary addition.In recent technology adder is a most priority one in all gadgets.The proposed design will have the capability to improve the Design metrics like speed, performance and reduced fan-out; here the proposed work implements a parallel self-timed adder with the aid of Verilog logic will achieve 8-Bit, 16-Bit, 32-Bit addition.Finally, this work will be designed in Verilog HDL and synthesized in Xilinx vivado FPGA and compared all the parameters in terms of area, delay and power.