Design of Compact Vedic Multiplier for High Performance Circuits
V. G. Pooja, B. S. Premananda, G. Ramesh · 2018
Multipliers are the major component in most of the processing units and DSP units. Due to the increasing limitations on delay, more importance is given to design of faster multipliers which do fast computations. Research is carried to find new techniques to increase multiplication speed and several modifications have also been made for Wallace tree, Baugh-Wooley and Booth algorithms. Among these multipliers, Vedic multipliers are presently one of the major fields in which research is carried out because they are fast. Urdhva Triyakbhyam (UT) is one among the sixteen Vedic sutras which is significant for multiplication. As power and speed are major concerns in designing multipliers. Quantum dot-Cellular Automata (QCA) is used, which are compact and consume less power. A 4×4 Vedic multiplier utilizing UT sutra in QCA technology is proposed. The design is realized using 2×2 multipliers as basic building blocks and partial product generated by addition using half adders and full adders. The proposed design is simulated using QCA Designer tool.