An Efficient Hardware Implementation of Radix-16 Montgomery Multiplication
Bien-Cuong Nguyen, Cong‐Kha Pham · 2019
This paper proposes a radix-16 modular Montgomery multiplication based on modified Booth-16 encoding. The Booth-16 encoding is modified to reduce the complexity and critical path-delay of the generation of partial products. The proposed algorithm is evaluated on Xilinx FPGA Virtex7 XC7VLX330T-3 with ISE 14.7. The hardware synthesis result shows that the proposed algorithm reduces both the cost and latency by 9.9% and 21.3% respectively, in comparison to the previous works.