Automatic MBIST Scheduling Engine
Kriti Sundar Das, Padmini Prakash · 2019
Due to shrinking technology node and demand for higher performance in an ASIC chip, SOC designs are becoming more and more memory intensive. Production testing of memories in SOCs on ATE is done by a memory BIST controller hardware engine embedded in the hardware. Implementation of BIST hardware is based on factors like clock frequency, physical location of memories and power domain considerations. Actual power efficiency of the MBIST implementation in SOC can only be found during ATE testing of silicon Devices. Simultaneous testing of all memories is often not possible due to dynamic voltage (IR) drop issues in the SOC. Current workaround is to test the MBIST controllers in strategic groups without having much of IR drop issues in different PVT conditions. This approach leads to increase in pattern volume and test time. DFT and ATE engineers have to spend considerable time and effort in this process. In this paper, we are proposing a novel idea, a method for automatically finding a working combination of MBIST controllers that can be tested simultaneously taking into consideration dynamic IR drop along with PVT variations. This new method reduces ATE and DFT engineer's time to bring up MBIST patterns for any SOC post-silicon validation. Since the grouping is done algorithmically, this solution saves test time and tester volume. The idea has been implemented as a hardware engine in SOC RTL and its experimental results are also shown in this paper. This automatic method makes use of JTAG interface to interact with the MBIST controllers, thus making it scalable to any SOC chip with JTAG based MBIST architecture.