Runtime Hardware Security Verification Using Approximate Computing: A Case Study on Video Motion Detection
Mengmei Ye, Xianglong Feng, Sheng Wei · 2019
The heterogeneous CPU-FPGA system architecture has been adopted in system-on-chip (SoC), server, and cloud computing platforms to achieve design flexibility and hardware-level performance acceleration. While benefiting the system performance, the newly added FPGA component in the traditional CPU-based computing platforms could result in undetectable system security issues via third-party FPGA IP cores that are produced by untrusted vendors. Traditional hardware and/or software security verification mechanisms do not suffice to address the unique security and runtime performance challenges introduced by the new system architecture. In this paper, we develop a novel approximate computing-based approach to achieve a fast and accurate enough repeated execution for security verification. We implement and evaluate the approximate computing-based security verification framework by conducting a case study on a CPU-FPGA based video motion detection system, in which our experiments on Xilinx Zynq SoC justifies the premium security and low performance overhead obtained by the proposed approach.