Reactive Signal Obfuscation with Time-Fracturing to Counter Information Leakage in FPGAs
Stephen M. Williams, Mingjie Line · 2020
With tremendous economic and technological ramifications, hardware security has become an increasingly more critical design metric for FPGA-based logic design. In this work, we focus on countermeasures against power side-channel attacks in any reconfigurable computing system implemented with modern FPGA fabric. We design and implement a novel countermeasure technique called Time-Fracturing (TF) to fend off side-channel-based information leakage, which proves to be both hardware-efficient and minimally invasive. To validate its effectiveness, we have applied our TF technique to an FPGA-based AES128 encryption core. Our experimental results have shown an increase of more than 50 times, when compared to its unprotected baseline, in its attack difficulty measured by the number of traces required to extract the secret key. Furthermore, our approach is orthogonal to existing methods, thus having the potential to be integrated in the future for a multi-variate defense mechanism.