Design of Reconfigurable Cache Memory Using Verilog HDL
K. N. Manjunatha, Kanagasabapati, Siva Sankar Yellampalli · 2018 International Conference on Electrical, Electronics, Communication, Computer, and Optimization Techniques (ICEECCOT) · 2018
Verilog Hardware Description Language is used to design cache memory which involves direct mapping and set associative cache. Further set associative cache involves two-way, four-way and eight-way. In this design of cache memory architecture, the mapping technique can be varied using controller unit. To increase accessing speed and optimize power by disable unused cache memory set blocks.