Design of High Speed AES System for Efficient Data Encryption and Decryption System using FPGA
Santhosh Kumar R, R Shashidhar, A M Mahalingaswamy, Praveen Kumar M S, M. S. Roopa · 2018 International Conference on Electrical, Electronics, Communication, Computer, and Optimization Techniques (ICEECCOT) · 2018
In the Security of Data Transmission Cryptography play an important role. The main aim is to increase the throughput of Advanced Encryption Standard algorithm through hardware technique by processing multiple rounds simultaneously. Main advantage of AES algorithm is to implemented in both software and hardware. Advanced encryption standard implemented in hardware because the hardware implementation has the advantages of increase throughput and offers better security. For the performance up gradation, the Field-Programmable Gate Arrays is one of the prominent solutions. The AES function calculation for encryption includes four transformation stages which are shift rows, sub bytes, add round key, Mix column. The AES function calculation for Decryption includes four transformation stages which are Invsubbytes, Invshiftrow, InvMixColumn, Invaddround key. An advanced encryption standard have developed and simulated in Spartan 6 FPGA and Development board is XC6SLX-9TQG144. In our proposed sequential AES design the operation frequency can reach 291.68MHz and throughput can be up to 37.21Gbps. Encryption, Decryption and FPGA are the three modules are implemented in AES Hardware implementation.