Multi-Core Architecture and Network on Chip: Applications and Challenges
Maddula N. V. Sesha Saiteja, K. Sai Sumanth Reddy, D. Radha, Minal Moharir · Journal of Computational and Theoretical Nanoscience · 2020
Technology improves performance and reduces in size day by day. Reduction in size can increase the density and which in turn can improve the performance. These statements suit very well for the computer architecture improvement. The whole System on Chip (SoC) brought the concept of multiple cores on a single chip. The multi-core or many-core architectures are the future of computing. Technology has improved in reducing the size and increasing the density, but improving the performance to an expectation of including more cores is a challenge of many-core technology. Utilization of all cores and improving the performance of execution by these cores are the challenges to be addressed in a many-core technology. This paper discusses the basics of many core architecture, comparison and applications. Further, it covers the basics of Network on Chip (NoC), architectural components, and various views of current Network on Chip research problems. Research problems include improving the performance of communication by avoiding congested path in routing.