Low Latency Scaling-Free Pipeline CORDIC Architecture Using Augmented Taylor Series
Sumit Satyavijay Wadkar, Bishnu Prasad Das, Pramod Kumar Meher · 2019
In this paper, we propose a low latency scalingfree CORDIC algorithm. The reduction of latency is achieved by suitable combination of multiple angles in different pipeline stages. The efficient use of trigonometric identities along with augmented Taylor series approximation and modified nanorotation in different stages make the CORDIC algorithm completely scaling-free. The comparison of FPGA implementation results with other CORDIC architectures in Xilinx SPARTAN 3E FPGA shows that the proposed architecture has significantly low slice-delay product with similar accuracy.