Network on Chip: A Review of Fault Tolerant Adaptive Routing Algorithm
N S Vindhya, B M Vidyavathi · 2018 International Conference on Electrical, Electronics, Communication, Computer, and Optimization Techniques (ICEECCOT) · 2018
Advanced VLSI technology eased accommodation of an increased number of IP modules on a single platform, leading to Networks-On-Chip (NOC). However, the IP Connecting links of NOC are liable to fault and congestion. Posing a route calculation challenge for communication. Optimized performance of NOC demands efficient adaptive routing algorithms. Many dynamically adaptive techniques designed over the years for better link utilization. In this paper, we discussa different type of link faultsand different adaptive routing algorithms. Further self-learning cognitive techniques and their impact on NOC performance are explored.