Efficient Hardware Verification Using Machine Learning Approach
Priyanshi Gaur, Sidhartha Sankar Rout, Sujay Deb · 2019
The current hardware verification techniques make use of pseudo-random number generators to induce test inputs. However, the randomization of some inputs can lead to an unexpected output, thereby causing failures. These failures are usually debugged by tracing back to the responsible input in the simulation waveform. Simulation-based debugging provides accurate and reliable results but incurs a huge computation overhead. In this work, we propose a low overhead machine learning (ML) based solution for debugging failures arising from randomization of inputs. Our approach involves training an ML model to predict the switching probability of the output without the knowledge of complete internal circuitry of the whole design. The predicted value of output switching probability is used to classify an input as randomizable or nonrandomizable. The ML model is trained on smaller datapath sub-circuits, and can then be used to make predictions on complex industrial designs consisting of any combination of training circuits.