An Efficient Reconfigurable FIR Filter for Dynamic Filter order variation
Bandreddi Ray Srinivasa Rao, B. Bala Tripura Sundari · 2019
FIR filter is main and important block in the digital signal processing applications. Even though several approaches for FIR filter designs proposed, because of increasing waste usage of digital applications and rapid growing in the VLSI industry still need and scope for to design a power and area efficient filter. In this paper proposed a novel scheme for the design of an area and power efficient digital finite impulse response (FIR) filter for future multi standard communications. The presented parallel architecture model supports run time variation of filter order and filter coefficients. In the design process discussed every block in detail mainly for faster computation time of the design selected faster multiplier and adder. To get the less hardware area and fast in computation time Vedic multiplier is used for the multiplication block and carry save adder is used for addition in the design. The proposed design can handle the length of 16-tap and 8-tap is and implemented in Verilog HDL. Implemented Verilog code for the design is verified by using simulation results and checked synthesis of the design in Vivado Xilinx IDE. The synthesizable code is compiled in Synopsys Design Compiler (DC) for Power and area calculations using SAED 90nm CMOS technology. The ASIC results shows the improvement in power 18.89% and 18.30% for 16-tap and 8-tap FIR filter respectively than the conventional method.