High-Speed Single Precision Floating Point Multiplier using CORDIC Algorithm
Balaji Yeshwanth, Vutukuri Venkatesh, Repala Akhil · 2018 International Conference on Electrical, Electronics, Communication, Computer, and Optimization Techniques (ICEECCOT) · 2018
Floating point arithmetic has paramount necessity in computer systems. Floating point multiplier is appreciably used in numerous applications which yearn for speed. Generally, floating point multiplier requires 23×23 mantissa multiplication and 8-bit exponent addition. Thus, delay of the mantissa multiplication plays a crucial role in boosting the speed. In this paper, the prime proposal is to increase the speed of the single precision floating point multiplier by implementing mantissa multiplication using CORDIC algorithm and exponent addition using Kogge-Stone adder which results in increasing the speed by several folds. Further, the performance of floating point multiplier using CORDIC algorithm and VEDIC multiplier is contemplated in terms of area, delay and power. Floating point multiplier was designed in VHDL using XILINX ISE 14.7 and implemented in XILINX Spartan 6e board. The proposed idea has shown better performance in terms of speed.