Heterogeneous Adder Based FIR Filter Design And Simulation
Admassu Admassu Assegie · International Journal of Informatics and Communication Technology (IJ-ICT) · 2020
The finite impulse response (FIR) is one of the important filters in digital signal processing (DSP) as it responds for a finite duration and settles to zero on the finite time. Digital FIR filters are programmable in nature and its behavior can be understood with the help of the program and can be easily programmed for the memory of a processor. The digital filters can be replaced without change of the hardware or the external circuitry. The 7 tap FIR filter needs 16 numbers of multipliers and 9 adders which are used in parallel form. The paper focused on the chip design and implementation of the FIR filter with a decimal adder and heterogeneous adder is done using VHDL programming in Xilinx 14.2 ISE software and the same is synthesized on SPARTAN - 3E FPGA to verify the results. Moreover, the functional simulation is done in Modelsim 10.0 software. Hardware utilization parameters, combinational path delay, memory utilization parameters are directly extracted from the Xilinx software for FIR filter architecture based on decimal adder and heterogeneous adders. The comparative analysis of the FIR filter is done with heterogeneous adder architecture lead an area and delay efficient design for DSP applications