Hardware Description Beyond Register-Transfer Level Languages
Oron Port, Yoav Etsion · 2020
Prevalent hardware description languages (HDLs), e.g., Verilog and VHDL, employ register-transfer level (RTL) as their underlying programming model. One major downside of the RTL model is that it tightly couples design functionality with timing and device constraints. This coupling increases code complexity and yields code that is more verbose and less portable. High-level synthesis (HLS) tools decouple functionality from timing and design constraints by utilizing constructs from imperative programming languages. These constructs and their sequential semantics, however, impede construction of inherently parallel hardware and data scheduling, which is crucial in many design use-cases.