RTRLib: A High-Level Modeling Tool for the Implementation of Dynamically Partial Reconfigurable System-on-Chips
Regina Marcela Ivo, Daniel M. Muñoz · 2019
Partial Reconfiguration allows the time-multiplexing resources to be explored, accomplishing requirements such as adaptability, robustness, power consumption, cost, and also fault tolerance. This paper presents a new partial reconfiguration toolkit called RTRLib that aims to simplify the development of dynamically reconfigurable systems, consequently reducing the development time. The RTRLib is a platform-based high-level modeling tool for run-time reconfigurable systems based on the semi-formal refinement-by-replacement methodology used to simulate and analyze the system behavior during the reconfiguration process. The RTRLib also automatically provides the Vivado and SDK scripts, under some restrictions. Since RTRLib is based on previous characterized IP-cores, it is possible to have an earlier estimation of the reconfiguration time and the reconfigurable partitions resource utilization during the design process. The proposed solution allows the designer to construct the partial reconfiguration solution to be mapped on FPGA-based System-on-Chips by a simple system specification and parametrization.