Cost-Efficient Adaboost-based Face Detection with FPGA Hardware Accelerator
Keng-Chia Chang, Chih‐Peng Fan · 2019
In this paper, a cost-efficient Adaboost-based hardware accelerator design is developed for face detection. For the realization, a lot of operations and fast calculations of the rectangular Haar features of partial image regions are required. To speed up the processing time for integral image and face detection functions, the hardware accelerator implementation is an important issue for real-time application. In experimental results, by Xilinx XC7a200t device at 205MHz operational frequency, the applied integral image accelerator performs up to 1161 frames/sec with the image size of 240×360 pixels. When the input ROI sizes are 80×80 and 64×64 pixels, the proposed Adaboost-based classifier operates up to 574 and 821 face ROIs/sec, respectively.