A New Robust Design of Dual-Rail Checker in QCA Technology, Capable of Testing of Digital Electronics Circuit
Dharmendra Kumar, Vinodhini Shankar, K Vittal · 2019 International Conference on Smart Systems and Inventive Technology (ICSSIT) · 2019
As metal-oxide-semiconductor (MOS) based devices and circuits faces glowingly physical barriers down the popularity and some constraints such as limitation of scaling, short-channel effect, and hot carrier effect, so innovative technique for the synthesis of circuits in Nano-scale have been developed to raise the popularity of computing. These Nano-computing techniques have shown good performance in term of speed, area and integration density. This article is devoted to the robust architecture of dual-rail checker using the co-planar technique in QCA Designer tool. These designs are of concern to modern testing approach. These circuits are also included a modern approach for physical implementation such as Quantum-Dot cellular automata. The main concern of this article is on the synthesis of nano computing testing circuit in QCA. The interest of this article is not only synthesis aspects it covers the physical implementation aspect also. Dual-rail checker is an inherent module of the testing digital logic circuit. High device density happens to be an important factor in the synthesis of the Dual-rail checker. The article proposed a robust architecture of Dual-rail checker using QCA Technology, which consumes a less number of quantum cell and latency. To tackle the fault during the computing, we have synthesis a novel dual-rail checker design for 4-dot, 2-electron based QCA architecture via co-planar technique.