Demonstration of On-Chip Test Decompression for EDT using Binary Encoded Neural Autoencoders
Philemon Daniel, Shaily Singh, Garima Gill, Anshu Gangwar, Bargaje Ganesh, Kaushik Chakrabarti · 2019
The ever-increasing test data and application time despite EDT is the motivation behind the search for a new technique. We propose a novel neural-network based test architecture for on-chip test decompression. The idea is to use binary and quaternary encoded dense autoencoders. The network is trained offline with inputs, outputs and weights quantized to one of the sets as in {-1, +1} or {-2, -1, +1, +2}. The network is then encoded into one or two-bit binary weights to be used as on-chip decompressor for EDT feeding into the scan chains. To aid the network to accurately reproduce the compressed bits - the network, loss, optimizer and activation functions are varied. Hardware implementation of the decompressor is demonstrated for stuck-at test patterns generated by ATPG as a minimal and scalable combinational logic. We also discuss on extending the technique using binary encoded convolutional neural networks and using binary recurrent neural network as output compactor. This is the very first effort to use neural network of any sorts for on-chip deterministic test generation.