Systematic Construction of Resistor Ladder Network for N-ary DACs
Manato Hirai, Shuhei Yamamoto, Hirotaka Arai, Anna Kuwana, Hiroshi Tanimoto, Yuji Gendai, Haruo Kobayashi · 2019
This paper describes a systematic configuration method of resistor ladder networks for N-ary DACs, by generalizing the configuration of the conventional R-2R DAC. Resistor networks divide the current at each node with its combined resistor ratio; the current flowing into each node of the resistor ladder is weighted with a non-binary ratio. Also using several unit current sources at each node, configuration of non-binary weighted DACs (such as ternary and quaternary weighted ones) can be derived. We have verified the operation of these resistor network DACs by SPICE simulations, and discuss their pros and cons as well as possible applications.