A fault manager for digital VLSI circuits
A. Lyoi, Mark J. Oreglia · Dialnet (Universidad de la Rioja) · 1988
This paper introduces the Fault Manager, an effective tool to generate targer fault sets for fault simulation and test pattern generation. Its innovative features are the uniform fault model for mixed-level circuits, a fast collapsing algoritm, and a flexible user-friend interface allowing different types of fault selection to be performed.