High performance adder's synthesis using efficient macro generator
T. Vassileva, V. Tchoumatchenko, V. Shishkov, Alain Guyot · HAL (Le Centre pour la Communication Scientifique Directe) · 1997
This paper presents a computer program for a fast adder's synthesis. From a given input operand size the program generates structural VHDL models of carry look ahead (CLA) or ripple-carry adders. In case of CLA adders the designer can select from several architectural variations of Brent-Kung adders. The synthesis target can be any standard cells library or a custom library with optimised "o" cells. The resulting VHDL code can be embedded in larger designs (e.g. signal processors) and used as input for logic synthesis tools.