Speeding up of Design Convergence using Spyglass
Ajmal Firdous, S. Kusuma · 2019 Global Conference for Advancement in Technology (GCAT) · 2019
In Today's modern world of ASIC designs which has high complexity and need high scale integration due to the fast pace development of the products which also creates high competition and demand for development of the product, crunch time to manufacture the products , It is necessary that product should be manufacture on time with the specified architecture with no defects ,if any defects are found in the tape the whole process of sorting out the defect is called Respin which is a huge loss in terms of time and money. This puts pressure on designer for good design work which requires greater need for RTL design coding and even greater simulation than the conventional way which can be achieved using SPYGLASS CDC. In this project by considering Lockstep counter as an example we are demonstrating that SPYGLASS requires less Run-time to report the bug as compared to Traditional Verification method.