Increasing MPSoCs design space with partial-ISA processors
Pedro Henrique Exenberger Becker, Jeckson Dellagostin Souza, Antonio Carlos Schneider Beck · 2019
Heterogeneous MPSoCs are key to meeting energy efficiency and performance under constrained scenarios since different cores and accelerators are combined. In this work, we propose a novel approach to expand MPSoCs' design space. By removing the microarchitectural support of costly ISA extensions (e.g., FP, SIMD, crypto) of some of the MPSoC processors, we make room to add extra processors or hardware accelerators to the system. We apply this methodology to the FP instructions of a conventional MPSoC environment and demonstrate up to 40% reduction in energy consumption (geomean) maintaining baseline performance, under area and power constraints.