Multi-Context TCAM Based Selective Computing Architecture for a Low-Power NN
Ren Arakawa, Naoya Onizawa, Jean-Philippe Diguet, Takahiro Hanyu · 2019
In this paper, we propose an energy-efficient hardware architecture that consists of multipliers and a non-volatile Multi-Context Ternary Content-Addressable Memory (MC-TCAM), where a CMOS/magnetic tunnel junction (MTJ) devices-hybrid circuit technique is used. If the input data stored in MC-TCAMs is appeared, the corresponding multiplication result is obtained from the MC-TCAM, resulting in the energy-efficiency. In addition, as the upper bits of the input data could be cut in a target application, the memory capacity of the MC-TCAM becomes small, which reduces power consumption in the MC-TCAMs. In case of speech command recognition, the proposed architecture reduces the power consumption by 45% at the multiplication of a CNN keeping the accuracy using TSMC 65-nm CMOS and a MTJ model.