Identification of Stuck-at-faults of Full Adder using FPGA as a Testing Device
P Vinopoornima, Gnanasekaran Dhanabalan · 2019 IEEE International Conference on Intelligent Techniques in Control, Optimization and Signal Processing (INCOS) · 2019
Advanced CMOS devices are a critical issue due to the shrinking process of the size of the transistor. The number of transistors packed in an IC increases with the latest technology. Manufacturing defects in the chip happen due to the interconnection of wires. This leads to unexpected outputs. The process of testing confirms that the chip is fault free. This work discusses the number of test vectors needed to find the faults present in a full adder. It is achieved with the help of a field programmable gate array (FPGA). An adder circuit is realized in FPGA. Test vectors are also implemented in FPGA which is fed as inputs to the full adder. Thus generated outputs are tested with the expected outputs to identify the faulty position(s) in the full adder. Virtex -5 LX50T FPGA chip was used to realize the testing.