Design and Implementation of Reconfigurable Polyphase Filter Bank Receiver on Artix-7 FPGA
Salauddin Mohammad, Durai Pandy, K. Snehalatha, Towheed sulthana · 2019 IEEE International Conference on Intelligent Techniques in Control, Optimization and Signal Processing (INCOS) · 2019
Digital Signal Processing (DSP) is always an emerging research area in the field of electronics. The objective of the paper is to design a digital FIR filter with polyphase filter bank receiver structure which can be used for band limiting applications [1]. The sampling frequency for the design is chosen to be fs:30 KHz and the other frequencies Fpass1: 4 KHz, Fstop1: 6 KHz, Fstop2: 12 KHz, Fpass2: 14 KHz keeping the density factor: 20. The filter designed is a Direct-Form FIR filter with Order: 36 and designed using Equiripple method. The common operations that include addition multiplication and delays have been also implemented in this paper which uses 3-level parallel multiplier structure. The proposed system gives best measures in speed, power consumption and the hardware utilization. Direct Digital Synthesizer (DDS) core has been used to generate a message signal of 1-MHz frequency and 16-bit sample, which is used to test the proposed FIR filter. The Carrier signal of 10-MHz with 16-bit sample is also generated to get the modulated signal and the same modulated signal is passed through the FIR filter at the receiver for the noise removal and the reconstruction of the original signal [2]. The simulation part is carried out on Xilinx ISE and Modelsim 10.1 using VHDL language. And the synthesis part is implemented and verified on Artix-7 FPGA using chipscope pro tool.