A System for Standard Cell Routability Checking and Placement Routability Improvements
I-Lun Tseng, Zhao Chuan Lee, Vikas Tripathi, Chun Ming Tommy Yip, Zhinan Chen, Jonathan Yoong Seang Ong · 2019
As semiconductor process technologies continue to advance, routability and pin accessibility of standard cells have become major concerns while physical layouts of standard cells are being designed. Although analytical-based methodologies have been proposed in the literature for rapid computations of cell routability and/or pin accessibility scores, physical synthesis tools are still needed in the verification of cell routability and/or pin accessibility since different physical synthesis tools can have very dissimilar P&R (placement and routing) behaviors and capabilities. In this paper, therefore, we propose techniques adopted in a software system, which uses a physical synthesis tool, for measuring the routability of individual and abutted standard cells, so that cells which have routability and/or pin accessibility issues for the tool can be detected. Moreover, the system is capable of generating cell spacing constraints for cell-edge pairs in order to improve routability of placed standard cell instances. Our system has been used in the detection of routability issues for many industrial standard cell libraries and for improving routability of placed designs. Experimental results show that DRC (design rule checking) violations in routed designs can be reduced after generated cell spacing constraints are applied.