A Bit-Segmented Adder Chain based Symmetric Transpose Two-Block FIR Design for High-Speed Signal Processing
Jinghao Ye, Masao Yanagisawa, Youhua Shi · 2019
A high-speed FIR filter structure is proposed in this paper by utilizing bit-segmentation adders and symmetric transpose 2-block FIR structure. First, a bit-segmented adder chain-based design is proposed with bit-segmentation adders. Second, a basic unit design of symmetric transpose block FIR is proposed to reduce the critical path delay. The evaluation results show that, when compared with state-of-the-art high-speed CSD multiplier-based FIR filter design, the proposed design requires 14.1% less area while provides 7.9% frequency improvement, 10.2% reduction of power consumption, 22.8% reduction of energy-delay-product and 20.4% reduction of area-delay-product, which shows the effectiveness of the proposed method.