Parallel Bit Pattern Computing
Henry Gordon Dietz · 2019
There are many ways to reduce power consumed in performing a computation. Most focus on making each gate more power efficient. In contrast, the current work focuses on directly reducing the number of gate-level operations needed to produce each word-level result. Compiler optimization of computations at the gate level exposes many redundancies that are not apparent when optimizing word-level operations. In the proposed architecture, all operations on multi-bit data values are performed bit serially. Thus, a k-bit add takes O(k) clock cycles. However, by doing each operation SIMD-parallel on n data, n k-bit operations also complete in O(k) clock cycles using only O(n) gates per clock. Further improvement can be made by using regular expression patterns to represent the n values in each bit position; not only does this compress the data, but it also allows many gate-level operations to be performed directly on the patterns without expanding them to bit vectors.