Hardware Acceleration of the AES Algorithm using Nios-II Processor
Argyrios Sideris, Theodora Sanida, Minas Dasygenis · 2019
Nowadays, cryptography plays a crucial role in both transmitting and receiving sensitive information, so that any unauthorized person does not have access to it. Advanced Encryption Standard (AES) is the most common symmetric encryption algorithm widely used in many applications. In this document, we present the implementation of the AES algorithm in Very High Speed Integrated Circuit Hardware Description language (VHDL) programming language with 128, 192 and 256 bit key sizes using the Nios II processor in the FPGA Arria 10 GX (10AX115N2F45E1SG). We implemented two techniques without custom instruction and with floating point 2. We compared in the two implementations the three AES key sizes in terms of integration time, number of cycle clocks, and the percentage of used hardware resources (LUTs used in the FPGA). The results have shown that, the larger key size, requires longer clock cycle and longer integration time as well. Implementation with Floating Point 2 shows over 11,07% acceleration in clock cycles and total time on all key sizes. The results of two implementations, are compared with existing similar designs and are found to achieve better performance.