A distinct carry celect adder design approach for area and delay reduction using modified full adder
K. Bala Sindhuri, G. S. Chandra Teja, K. Madhusudhan, N. Udaya Kumar · 2019
A SQRT Carry Select Adder (CSLA) design with modified full adder architecture is proposed in this work. The regular SQRT CSLA has less delay but it is bulky when compared with other adders. The proposed design has reduced area and delay for a SQRT CSLA. The architecture is designed for a 128bit and is synthesized, simulated in Vivado v2017.2 software. The result concludes that the new design is giving a considerable amount of reduction in area and delay. Also, the proposed design is of 128-bit therefore it can be used in the future designs of efficient processor.