FPGA-based Task Scheduler for Mixed-Criticality Real-Time Systems
Lukáš Kohútka, Viera Stopjaková · 2019
Mixed-criticality real-time systems represent an emerging technology that faces many research issues. In this paper, a new coprocessor unit that realizes FPGA-accelerated task scheduling for mixed-criticality real-time embedded systems consisting of tasks of various deadlines, priorities and criticalities is presented. We propose an FPGA-based task scheduler that implements an existing algorithm called Robust Earliest Deadline and previously developed hardware architectures used for scheduling of real-time tasks that implement other algorithms. Due to the hardware implementation of the scheduler, the duration of scheduler operations is always constant (2 clock cycles) regardless of the task amount within the system. The proposed scheduler was verified by simulations that applied millions of random inputs. Resource costs of the proposed solution are evaluated within an Intel Cyclone V FPGA synthesis. Two versions of task schedulers were compared and analyzed: existing EDF scheduler applicable for hard RT tasks only and the proposed RED scheduler. According to synthesis results, the proposed solution consumes 235% to 397% more look-up tables and 44 % to 171 % more registers than the EDF scheduler with equivalent parameters used. However, the proposed scheduler provides performance and can handle any combination of non-RT, soft RT and hard RT tasks together in the same system, which is achievable by state of the art.