System Level Communication Challenges of Large FPGAs
Mustafa Abbas · TSpace (University of Toronto) · 2019
As FPGA capacity and the complexity of the designs implemented on them have grown, so too have system-level communication challenges. At the design level the typical latency of long distance interconnect grows making them the limiting factor in reaching timing for a design. We explore the use of latency-insensitive design (LID) as a solution. Our best approach gained 2x area efficiency and 18\% less critical path delay over traditional LID, and come at a minimal speed overhead of 3\% compared to a latency-sensitive design. At the architecture level the number of clocks has grown. It is challenging to supply global clocks to all modules efficiently. Therefore, the clock architecture must be flexible to allow for smaller and more power efficient networks to be built. We present a flexible clock modeling format, built into open source CAD tool VPR, to allow clock impacts and architecture options to be explored.