Optimization of FPGA Routing Networks with Time-Multiplexed Interconnects
Ruiqi Luo, Xiaolei Chen, Yajun Ha · 2020
In FPGA chips, interconnects occupy a large part of the timing and area consumption. Previous work on time-multiplexed FPGAs inspires us to apply the time-multiplexing technique to FPGA interconnects. To support this new architecture with time-multiplexed interconnects, we propose a routing algorithm that is time-multiplexing aware. This algorithm is similar to the VPR 5 routing algorithm, but this algorithm can also identify nets that can be scheduled to reuse. We validate the algorithm experimentally by implementing it as a multiplexing aware router and using this router to implement benchmark circuits to FPGAs with time-multiplexed interconnects. The results show that compared with an existing router targeting a conventional island-style architecture, 20% smaller minimum channel width and 10% smaller circuit critical path delay can be achieved.