Design of an Improved Fault Coverage Programmable Pseudorandom Pattern Generator for Bist
Gaddam Shravan Kumar, Chakradhar Adupa · Apple Academic Press eBooks · 2019
This project presents a Low power programmable pseudo-random pattern generator which is more suitable for built in self test (BIST) structures used for testing of VLSI circuits. The purpose of the BIST is to reduce power dissipation without affecting the fault coverage. This LP-programmable pseudorandom pattern generator produce pseudo random test patterns with desired toggling level and also enhanced fault coverage compared with other BIST PRPG. It comprised of finite state machine LFSR driving a phase shifter and it allows the device to produce binary sequence with preselected toggling activity. Generator is automatically controlled providing easy and precise tuning. Furthermore, this project introduces a test compression method to avoid repeated pattern generation for testing the same device.