Development of SDC–SDF Architecture for Radix-2 FFT
G. Deeshma Venkatakanakadurga, G. R. L. V. N. Srinivasaraju · Apple Academic Press eBooks · 2019
In this chapter, we propose a single-path delay commutator (SDC)–feedback (SDF) architecture for Radix-2 fast Fourier transform (FFT) and presented its simulation results. The Radix-2 FFT architecture includes one SDF stage and log 2 N-1 SDC stages. The SDC processing engine is used to attain 100% hardware blocks utilization by using the common arithmetic resources in the time multiplexed approach, including the architectures adders and multipliers. To get output sequence in normal order, we also have a bit reverser block; through this we can reduce 50% memory usage. The resultant architecture is simulated and design verification was done by using the software ModelSim and XilinxISE. The proposed architecture was achieved with reduced area and delay as well as improved performance.