Implementation of a New VLSI Architecture for Add–Multiply Operators using a Modified Booth Recoding Technique
K. Nunny Praisy, K. S. N. Raju · Apple Academic Press eBooks · 2019
The alternate operations are used to modify the applications in the digital signal processors. Mainly we will design the modified booth recoder with the sum of two numbers to increase their performance. The main operation that is performed in this technique is multiply and Accumulator (MAC) which is used to increase the performance in digital signal processor. This is mainly done with Fused Add Multiply (FAM) to reduce the critical path, power dissipation and area. This is introduced for the performance of the carry look-ahead adders (CLA) to reduce the Area-delay of the design with reversible logic gates.