Implementation of an Efficient Reverse Compressor Multiplier and Adder Based MAC Architecture
K. Sreenath, H. Chandrasekhar · Zenodo (CERN European Organization for Nuclear Research) · 2018
Power dissipation is recognized as a critical parameter in modern VLSI design field. To satisfy MOORE'S law and to produce consumer electronics goods with more backup and less weight, low power VLSI design is necessary. High speed and low power Multiplier-Accumulator (MAC) units are required for applications of digital signal processing like Fast Fourier Transform, Finite Impulse Response filters, convolution etc.The proposed MAC uses multiplier with reverse compressor design multiplier and adders as primitive building blocks for efficient application. Further, the Verilog-HDL coding of MAC architecture and their implementation by Xilinx ISE 14.3 SynthesisTool. The proposed reverse compressor multiplier and adder based architecture used to be applied to MAC unit and in comparison to the previous design MAC unit and verified that the proposed architecture have reduce interms of delay.