Design a floating-point fused add-subtract unit using verilog
Mayank Sharma, Aswani Sengar, Prince Nagar · Archives of applied science research · 2013
A floating –point fused add subtract unit is described that performs simultaneous floating –point add and subtract operations on a common Pair of single –precision data in about the same time That it takes to performs a single addition with a Conventional floating –point adder. Placed and routed in 45nm process. So that there will be less consumption of memory as well as power.