Efficient FIR Upsample Circuit
Yong-Eun Kim · Journal of the Institute of Electronics Engineers of Korea · 2009
FIR upsampling circuit generates output data L times faster than input data. For efficient implementation of upsampler, FT filter stages Noble identity theory. In this paper, we propose a method that one of the divided filter stages is removed by making Phase delay to integer number. 192taps 2-times upsampler used in CDtoDAT is designed using proposed method. The designed circuit is synthesized using Hynix 0.18um process. By the simulation results, it is shown that the proposed method leads to up to 48%, 43% and 99.9% and 68% reduction in area, power consumption and maximum phase delay error and maximum ripple error compared with conventional method.