A Designed DES Chip with CPLD Technology
Narong Buabthong, Somchart Chokchaitam, Surachai Hirinitichai, Kanok Musickmas · Thammasat International Journal of Science and Technology · 1997
This paper presents a designed DES chip with CPLD technology. The DES chip is synthesized and simulated by using AHDL technology. Three MAX9000 chips are used for DES algorithm by using 1388 logic cells,86% utilization, 123-input pins, and 64-output pins.